FIG. 1 shows a simplified block diagram of an EPLD 100. EPLDs typically include two or more functional blocks (FB) 110 connected to receive input signals on FB input lines 115 from an interconnect matrix 120. Each function block 110 is made up of a number of macrocells (discussed below) which transmit output signals to input/output (I/O) blocks 130 on output lines 125. In addition, feedback signals from each macrocell are transmitted to interconnect matrix 120 on feedback lines 135. Finally, input signals are transmitted from I/O block 130 on input lines 145.
FIG. 2 shows in additional detail how signals are passed to and from I/O blocks 130 in Xilinx XC7000 series EPLDs, which are described in additional detail in Section 3 of the 1994 Xilinx Programmable Logic Data Book, which is incorporated by reference herein. Data signals generated in interconnect matrix 120 are transmitted on FB input lines 115 to function blocks 110. Output enable lines 155 transmit control signals for switching the appropriate circuitry of I/O block 130 such that macrocell output signals are transmitted to I/O pins 150. In XC7000 series EPLDs, each function block 110 typically includes nine macrocells, the outputs from which being selectively transmitted to I/O block 130 via output lines 125 and to interconnect matrix 120 on feedback lines 135, this transmission being controlled by output enable (OE) signals present on output enable lines 155.
FIG. 3 shows macrocell 160 and I/O block 130 in further detail. Only feedback control circuitry of macrocell 160 is described herein--a description of the input and logic producing portions of macrocell 160 are omitted. FIG. 3 shows an output control portion 130A and an input control portion 130B of I/O block 130 which are associated with an I/O pin 151. All of the circuitry shown in FIG. 3 is used in Xilinx XC7000 series EPLDs, and is explained in additional detail in the 1994 Xilinx Programmable Logic Data Book.
In the following description, individual signal lines are indicated by parenthesized digits. For example, one of the nine FB output lines 125 (see FIGS. 1 and 2) is identified by "125(1)".
Referring to FIG. 3, output signals from macrocell 160 are transmitted on output line 125(1) to I/O pin 151. Output control stage 130A receives control signals on a global fast output enable (OE) line and from output enable line 155(1). Based on these control signals, output control stage 130A controls a switch 131, which in turn controls transmission of the output signal from output line 125(1) to I/O pin 151. For example, when the output enable signal on output enable line 155(1) is low, switch 131 is turned off, and output signals on output line 125(1) are blocked by switch 131 from being transmitted to I/O pin 151. In this state, I/O pin 151 may be used to input signals into the interconnect matrix through the input control stage 130B on input line 145(1). Details regarding portions of output control state 130A and input control stage 130B which are not described herein can be found in the 1994 Xilinx Programmable Logic Data Book.
Referring to macrocell 160, feedback to the interconnect matrix is controlled by a switch 161 which, in turn, is controlled through an OR gate 163 by an output enable signal transmitted on output enable line 155(1), and by the programmed state of a feedback enable EPROM cell 162. For example, if the output enable signal on output enable line 155(1) is high, then switch 161 is turned on and the output signal on output line 125(1) is fed back to the interconnect matrix via feedback line 135(1). This feedback also occurs when feedback control EPROM cell 162 is programmed to apply a high signal to switch 161.
Several EPLDs, such as XC7000 series EPLDs produced by Xilinx, Inc. of San Jose, Calif., incorporate "cross-point" interconnect matrices in which every wordline is programmably connectable to every bitline, much like the programmable AND planes of a PAL. The "cross-point" type of interconnect matrix is described in U.S. Pat. No. 5,028,821, and is also described in co-owned U.S. application Ser. No. 08/430,207, filed Apr. 26, 1995, entitled "CROSS-POINT INTERCONNECT STRUCTURE WITH REDUCED AREA" [Attorney Docket Number X-143/M-3077], which is incorporated herein in its entirety. An advantage of cross-point interconnect matrices is 100% routability--that is, every wordline can be connected to every bitline within a cross-point interconnect matrix.
FIG. 4 shows a known sense amplifier 170 used in a cross-point interconnect matrix 120. The operation of this sense amplifier is described in the Background section of co-owned U.S. application Ser. No. 08/459,066, filed Jun. 2, 1995, entitled "SENSE AMPLIFIER FOR PROGRAMMABLE LOGIC DEVICE HAVING SELECTABLE POWER MODES" [attorney docket X-152-1/M-3372], which is incorporated herein in its entirety. Therefore, the following description will be limited to specific portions of sense amplifier 170 which are relevant to the invention described below.
Referring to FIG. 4, each sense amplifier 170 of interconnect matrix 120 is associated with one bitline BL, and transmits one product term from bitline BL to the AND array (see FIG. 3) of a function block on one of the FB input lines 115. As shown in FIG. 4, each wordline WL1 through WLn is selectively connectable through an EPROM 171 to bitline BL. In addition, each wordline WL1 through WLn is connected to one feedback line 135 or one input line 145. As such, every feedback line 135 and every input line 145 connected to one of the wordlines WL1 through WLn is selectively connectable to every FB input line 115 through cross-point interconnect matrix 120.
Signals on wordlines WL1 through WLn are selectively transmitted to bitline BL (in an inverted form) via EPROMs 171-1 through 171-n. For example, if EPROM 171-1 is erased (conductive), then a high signal on wordline WL1 turns on EPROM 171-1, thereby creating a low signal on bitline BL by connecting bitline BL to virtual ground VG through EPROM 171-1. Conversely, if EPROM 171-1 is programmed (non-conductive), then high signals on wordline WL1 will not turn on EPROM 171-1.
Long time users of EPLDs are aware of coupling noises in the interconnect matrix when multiple unrelated word lines are switching concurrently. The inventors of the present application have determined that this noise occurs in part because of two primary phenomenons: a) capacitive coupling between word lines and bit lines of the interconnect matrix, and b) noise on the internal Vcc and Vss power buses because of excessive concurrent wordline switching.
Capacitive coupling occurs, for example, when word lines connected to feedback lines from the macrocells are simultaneously shifted from high to low, or from low to high voltage potentials. As an example, when several macrocells of an EPLD implement a counter, the output signals from all of these macrocells switch from high to low when the counter "turns over" (i.e., every macrocell simultaneously shifts from a "1" to a "0"). In addition, the counter is typically driven by a common clock signal, so that all of the macrocells switch concurrently. This concurrent multiple macrocell switching event causes a large capacitive effect (coupling) between the bitlines and wordlines of the EPLD, thereby resulting in bitline noise.
Noise also occurs on the internal Vcc and Vss power buses when a large number of wordlines are switched simultaneously from high to low, or from low to high. Simultaneous switching creates a crowbar effect which causes large fluctuations in the voltage level of the power buses.